Computing devices typically comprise a processor, memory, and an external memory controller to provide the processor as well as other components of the computing device with access to the memory. The performance of such computing devices is strongly influenced by the memory bandwidth. Memory bandwidth may be increased and overall memory performance increased by providing a memory controller with multiple memory channels. For example, a memory controller with two memory channels has twice the available memory bandwidth and potentially twice the performance of a memory controller with only a single memory channel. However, memory controllers with multiple memory channels generally do not effectively utilize the additional bandwidth. In particular, such memory controllers typically allow one or more memory channels to experience substantial idle periods despite the processor having memory transactions that need to be serviced. Accordingly, computing device performance may be improved by reducing the frequency and/or duration of memory channel idle periods.